1. Field of the Invention
This invention relates generally to an arithmetic logic unit (ALU), and more particulary to an eight-bit expandable ALU for performing binary and binary coded decimal (BCD) arithmetic and various logic and transfer operations while incurring only four gate delays.
2. Description of the Prior Art
The semiconductor industry is constantly faced with demands for large scale integrated circuits (LSI) having expanded capabilities and higher operational speeds. For example, modern ALU integrated circuits must perform a variety of functions including binary and BCD addition and subtraction and a number of logic and transfer operations (e.g. shift right, shift left, invert, etc.).
One such multipurposed ALU (an LSI four-bit ALU slice) is manufactured by Motorola Semiconductor Products, Inc. and bears part number MC10800. This ALU has the capability of performing logic operations, binary arithmetic and BCD arithmetic on combinations of one, two or three variables. It incorporates a nine's complement circuit to generate the necessary BCD complement function and generates group propagate and generate signals which are used for external look-ahead carry between four-bit slice circuits. A carry-in (Cin) signal interconnects four-bit slice circuits and is used for both binary and BCD arithmetic operations. A carry-out (Cout) signal indicates that a calculated value in the ALU has exceeded the maximum capacity of the four ALU output lines.
The above described device uses the conventional BCD addition algorithm to perform subtraction; i.e., forming the nine's complement of the subtrahend. The binary sum is then corrected to obtain the BCD sum. This approach not only requires a large number of logic elements, but also involves a large number of logic stages of delay between the ALU inputs and outputs.
In an article entitled "High Speed Decimal Addition" by Martin S. Schmookler at al, IEEE Transactions on Computers, Vol, C-20, No. 8 August 1971, pages 862-865, there is described a design for a high speed and economical decimal adder wherein there is produced decimal sums without first producing the corresponding binary sums. However, this decimal unit does not include binary arithmetic capabilities.